Reliability Study of Combinational Circuitsy

Statistical Estimation of the Switching Activity in VLSI Circuitsy

Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these problems are directly related to the extent of circuit switching activity. The average number of transitions per second at a circuit node is a measure of switching activity that has been called the transition density....

Formal reliability analysis of combinational circuits using theorem proving

Reliability analysis of combinational circuits has become imperative these days due to the extensive usage of nanotechnologies in their fabrication. Traditionally, reliability analysis of combinational circuits is done using simulation or paper-and-pencil proof methods. But, these techniques do not ensure accurate results and thus may lead to disastrous consequences when dealing with safety-cri...

A STUDY ON THE MAXIMUM SPEED AND RELIABILITY ASSURANCE IN WAVE PIPELINE-BASED COMBINATIONAL CIRCUITS By

Methods and Metrics for Reliability Assessment

This paper deals with digital VLSI design aspects related to reliability. The focus is on the problem of reliability evaluation in combinational logic circuits. We present some methods for this evaluation that can be easily integrated in a tradidional design flow. Also we describe suitable metrics for performance estimation of concurrent error detection schemes.

Exploring the feasibility of selective hardening for combinational logic

In this work we introduce a cost-aware methodology for selective hardening of combinational logic cells, which provides a list of the most effective candidates for hardening. Two heuristics are proposed in order to define when selective hardening becomes unfeasible. The methodology and the heuristics are applied to a set of benchmark circuits using costs extracted from an actual standard cell l...